An amplifier component, especially a high-frequency amplifier component, within a chip housing with a compensation element, can be used in communications technology, for example, for the transmission of radio and television signals, in mobile-radio base stations, in computer measurement technology and for scientific purposes in order to generate large high-frequency powers.
The amplifier component is composed substantially of power transistors, which should operate, for example, over several octaves dependent upon the application. The power of the transistor in this context is relatively higher the lower the connected toad resistance. With transistor powers, for example, from 100 W to, for example, 1000 W, the load resistance is disposed within a range from several ohms down to below one ohm. This load resistance must be transferred via a matching network to a system impedance of typically 50 ohms. A parasitic capacitance, which limits the bandwidth of this matching network, is formed at the output of the amplifier component. This parasitic capacitance can be compensated by a compensation element which must provide an inductive behavior. A compensation element of this kind is generally formed by a small shunt inductance which is integrated into the amplifier component.
An amplifier component which provides two bipolar transistors which are arranged in a “push-pull” configuration (push-pull configuration), is known from U.S. Pat. No. 4,107,728, wherein transistor dies (transistor dies), or transistor chips (semiconductor elements) are accommodated in a common chip housing (housing of a semiconductor amplifier). U.S. Pat. No. 4,107,728 is incorporated herein by reference in its entirety. In this context, the parasitic output capacitance is formed between the collector surface and the reference ground, to which the two emitters are also connected. In order to compensate this parasitic output capacitance, a shunt inductance is formed, which connects both collector surfaces to one another within the chip housing. The shunt inductance itself is formed by a thin strip of metal.
The disadvantage with U.S. Pat. No. 4,107,728 is that a relatively large and expensive chip housing forms are necessary for the realization of such an integrated shunt inductance. Furthermore, the shunt inductance extends in places parallel to the bond wires which connect the transistor die to the connecting pins of the collector, thereby forming a coupling. The mutual inductance resulting from the coupling has a disadvantageous effect on the compensation behavior, so that, ultimately, the bandwidth of the matching network is reduced. Moreover, such a shunt inductance which is realized as a printed conductor cannot be applied directly to the flange, but requires an additional insulating layer. Such an insulating layer, which is typically formed from a ceramic or a substrate, is in fact necessarily present with the use of bipolar transistors or DMOS transistors (diffused metal oxide semiconductor; diffused metal oxide semiconductor), however, such an insulating layer is not necessary with the use of other types of transistors and must therefore be additionally applied for this shunt inductance. Thus, there is a need to overcome the aforementioned disadvantages.